Non-volatile semiconductor memory devices are currently used extensively through the electronics industry. One type of non-volatile semiconductor memory devices employs the use of floating gate memory cells that are able to retain and transfer charge through a variety of mechanisms which include avalanche injection, channel injection, tunneling, etc. A flash memory device is such a semiconductor device that utilizes a floating gate memory cell. As is the case with most semiconductors being fabricated, the industry continues to push for smaller devices that contain a larger number of memory cells than each previous generation. This is also the case for the flash memory device.
In a flash memory device, fabrication of the components that make up the floating gate transistor determines the ability of the device to be programmed and retain an electrical charge as well as the ability of the device to be reprogrammed by being erased (or the removal of the electrical charge). Flash memory cells comprising floating gate transistors are laid out in such a manner that a plurality of cells forms a memory array.
A device in the programmed state, i.e., charge stored on the floating gate, represents a stored “0” and a device in the non-programmed state, i.e., no charge stored on the floating gate, represents a stored “1.” Reading a device in the programmed state will cause the device to conduct heavily, while reading a device in the non-programmed state the device will not conduct. Each floating gate transistor in the array has a common source line and the common source line requires sophisticated fabrication techniques.
The present invention provides a flash memory cell structure and method to fabricate a floating gate device having a self-aligned floating gate, a low resistant local interconnect to the source and a self-aligned drain electrode contact plug, all of which will provide enhanced operation of a flash memory cell device.